1. Field of the Invention
The present invention relates generally to integrated circuits and multilayer structures for fabricating integrated circuits. More particularly, the invention relates to particular multilayer structures and methods of fabricating multilayer structures using modified oxide layers to improve hot carrier reliability in MOS devices.
2. State of the Art
The continual reduction of MOS device size has led to device reliability concerns. For example, failure to proportionally scale down the electric fields involved has reduced device reliability. Further, shrinking geometries have led to increased use of plasma-assisted etching and deposition processing for multilevel interconnect schemes. These plasma assisted processes can also lead to device instability and poor hot electron reliability.
For example, topside passivation layers of plasma enhanced chemical vapor deposition (PECVD) oxide and PECVD nitride have commonly been used to protect IC devices from external sources of device degradation such as sodium ions and moisture. However, the susceptibility of integrated circuits (ICs) to internal sources of device degradation such as charge buildup, charge trapping and the electric fields induced due to backend processing (i.e., fabrication of metallization layers for interconnections) has not been adequately addressed.
Past studies such as those described in the article by M. Chen et al, IEEE Trans. Elec. Device, Vol. 35 No. 12, 2210 (1988) have shown that silicon nitride passivation layers (e.g., PECVD plasma silicon nitride) used for passivation and reactive ion etch (RIE) of metal layers worsen hot electron effects (e.g., decreases hot carrier lifetimes). Similarly, the use of spin-on-glass (SOG) as part of the intermetal oxide decreases hot carrier lifetimes. Further, water adsorption in PECVD oxides and SOG result in generation of positive mobile charges with degradation of hot carrier lifetimes as described in N. Lifshitz et al, J. Electrochem Soc., vol 136, 1440 (1989) and N. Lifshitz et al, IEEE Elec. dev. Lett. vol 12, 140 (1991). In addition, the use of carbon based SOG in intermetal oxide leads to field inversion as described in D. Pramanik et al, Proc. of IEEE VMIC, 454, (1989). Also charge loss in EPROMS has been attributed to mobile positive ion generation in the interlevel dielectric as described by G. Crisenza et al, Proc. of IEEE IEDM, 107 (1990). These origins of device degradation are internal rather than external.
In pursuing techniques for reducing device degradation such as hot carrier effects due to internal sources, hot carrier effects have been divided into three general areas: hot carrier generation, hot carrier injection and hot carrier trapping. In general, hot carrier generation and injection are determined by device structure (i.e., electrical field intensity developed within the device) while hot carrier trapping is dependent on the integrated circuit fabrication processes and dielectric properties.
MOS device structures have been modified in the past to reduce hot carrier effects. For example, lightly doped drain (LDD) structures have been used to improve hot carrier lifetimes for sub-micron devices by reducing the electric fields generated. Although such modified device structures do reduce device degradation, the use of plasma processes and SOG layers in the backend processing can still significantly degrade hot carrier lifetimes for all types of device structures.